Technical Field
The present invention relates generally to semiconductor devices, and more specifically, to forming a sacrificial endpoint layer for deep shallow trench isolation (STI) recess.
Description of the Related Art
A typical semiconductor device in a complementary metal-oxide-semiconductor (CMOS) circuit is formed in a p-well or an n-well in a semiconductor substrate. Since other semiconductor devices are also present in the semiconductor substrate, a given semiconductor device requires electrical isolation from adjacent semiconductor devices. Electrical isolation is provided by isolation structures that employ trenches filled with an insulator material (e.g., shallow trench isolation or “STI” regions). The electrical isolation of a semiconductor device from other devices located in the same well is referred to as “intra-well” isolation. In contrast, the electrical isolation of a semiconductor device from other devices in an adjacent well (typically of the opposite polarity type, but could also be a same polarity type well of a different well bias) is referred to as “inter-well” isolation. In either case, the unintended functionality of parasitic devices needs to be suppressed. This is typically done by placing a dielectric material, such as an STI structure, in the current paths of the elements of the parasitic devices.